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256 MBit Synchronous DRAM
HYB 39S256400/800/160T
Preliminary Information
* High Performance: -8 -8B 100 10 6 12 7 -10 100 10 7 15 8 Units MHz ns ns ns ns * Multiple Burst Read with Single Write Operation * Automatic and Controlled Precharge Command * Data Mask for Read/Write control (x 4, x 8) * Data Mask for byte control (x 16) * Auto Refresh (CBR) and Self Refresh * Suspend Mode and Power Down Mode * 8192 refresh cycles/64 ms 7,8 * Random Column Address every CLK (1-N Rule) * Single 3.3 V 0.3 V Power Supply * LVTTL Interface versions * Plastic Packages: P-TSOPII-54 400mil width (x 4, x 8, x 16) * -8 part for PC100 2-2-2 operation -8B part for PC100 3-2-3 operation -10 part for PC66 2-2-2 operation
fCK tCK3 tAC3 tCK2 tAC2
* * * *
125 8 6 10 6
Fully Synchronous to Positive Clock Edge 0 to 70 C operating temperature Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2, 3, 4
* Programmable Wrap Sequence: Sequential or Interleave * Programmable Burst Length: 1, 2, 4, 8
The HYB 39S256400/800/160T are four bank Synchronous DRAM's organized as 4 banks x 16 MBit x 4, 4 banks x 8 MBit x 8 and 4 banks x 4 MBit x 16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS' advanced 256 MBit DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a single 3.3 V 0.3 V power supply and are available in TSOPII packages.
Semiconductor Group
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1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
Ordering Information Type LVTTL-Version HYB 39S256400T-8 on request P-TSOP-54-2 400 mil 125 MHz 4B x 16 M x 4 SDRAM PC100-222-620 P-TSOP-54-2 400 mil 100 MHz 4B x 16 M x 4 SDRAM PC100-323-620 P-TSOP-54-2 400 mil 66 MHz 4B x 16 M x 4 SDRAM PC66-222-820 P-TSOP-54-2 400 mil 125 MHz 4B x 8 M x 8 SDRAM PC100-222-620 P-TSOP-54-2 400 mil 100 MHz 4B x 8 M x 8 SDRAM PC100-323-620 P-TSOP-54-2 400 mil 66 MHz 4B x 8 M x 8 SDRAM PC66-222-820 P-TSOP-54-2 400 mil 125 MHz 4B x 4 M x 16 SDRAM PC100-222-620 P-TSOP-54-2 400 mil 100 MHz 4B x 4 M x 16 SDRAM PC100-323-620 P-TSOP-54-2 400 mil 66 MHz 4B x 4 M x 16 SDRAM PC66-222-820 Ordering Code Package Description
HYB 39S256400T-8B on request HYB 39S256400T-10 on request HYB 39S256800T-8 on request
HYB 39S256800T-8B on request HYB 39S256800T-10 on request HYB 39S256800T-8 on request
HYB 39S256800T-8B on request HYB 39S256800T-10 on request
Pin Description and Pinouts CLK CKE CS RAS CAS WE A0 - A12 BA0, BA1 Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select DQ Data Input/Output Power (+ 3.3 V) Ground Power for DQ's (+ 3.3 V) Ground for DQ's Not Connected
DQM, LDQM, UDQM Data Mask
VDD VSS VDDQ VSSQ
NC
Semiconductor Group
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HYB 39S256400/800/160T 256 MBit Synchronous DRAM
TSOPII-54 (10.16 mm x 22.22 mm, 0.8 mm pitch)
0.10.05
10.05
155
10.160.13 2)
0.8 155 0.35 +0.1 -0.05
3)
0.15 +0.06 -0.03
0.5 0.1 11.76 0.2
26x 0.8 = 20.8
0.1 54x 0.2 M 54x
54
28
6 max
1 2.5 max 22.220.13 1) Index Marking
1) 2)
27
GPX09039
Does not include plastic or metal protrusion of 0.15 max per side Does not include plastic protrusion of 0.25 max per side 3) Does not include dambar protrusion of 0.13 max per side
Pin Configuration for x 4, x 8 & x 16 organized 256 M-DRAMs
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HYB 39S256400/800/160T 256 MBit Synchronous DRAM
Column Addresses A0 - A9, A11, AP BA0, BA1 Column Address Counter Column Address Buffer
Row Addresses A0 - A12, BA0, BA1 Row Address Buffer Refresh Counter
Row Decoder
Row Decoder
Row Decoder
Row Decoder
Sense Amplifier & I(O) Bus
Sense Amplifier & I(O) Bus
Sense Amplifier & I(O) Bus
Bank 0
Bank 1
Bank 2
Sense Amplifier & I(O) Bus
Column Decoder
Column Decoder
Column Decoder
Column Decoder
Memory Array
Memory Array
Memory Array
Memory Array Bank 3
8196 x 2048 x 4 Bit
8196 x 2048 x 4 Bit
8196 x 2048 x 4 Bit
8196 x 2048 x 4 Bit
Input Buffer
Output Buffer
DQ0 - DQ3 Control Logic & Timing Generator
CLK CKE CS RAS CAS WE DQM V REF*) *) on SSTL versions only
SPB03781
Block Diagram for 64 M x 4 SDRAM (13/11/2 addressing)
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HYB 39S256400/800/160T 256 MBit Synchronous DRAM
Column Addresses A0 - A9, AP, BA0, BA1 Column Address Counter Column Address Buffer
Row Addresses A0 - A12, BA0, BA1 Row Address Buffer Refresh Counter
Row Decoder
Sense Amplifier & I(O) Bus Sense Amplifier & I(O) Bus
Row Decoder
Sense Amplifier & I(O) Bus
Row Decoder
Sense Amplifier & I(O) Bus
Row Decoder Memory Array Bank 3
Column Decoder
Column Decoder
Bank 0
Bank 1
Column Decoder
Bank 2
8192 x 1024 x 8 Bit
8192 x 1024 x 8 Bit
8192 x 1024 x 8 Bit
Column Decoder
Memory Array
Memory Array
Memory Array
8192 x 1024 x 8 Bit
Input Buffer
Output Buffer
DQ0 - DQ7 Control Logic & Timing Generator
CLK CKE CS RAS CAS WE DQM V REF *) *) on SSTL versions only
SPB03780
Block Diagram for 32 M x 8 SDRAM (13/10/2 addressing)
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HYB 39S256400/800/160T 256 MBit Synchronous DRAM
Column Addresses A0 - A8, AP, BA0, BA1 Column Address Counter Column Address Buffer
Row Addresses A0 - A12, BA0, BA1 Row Address Buffer Refresh Counter
Row Decoder
Sense Amplifier & I(O) Bus Sense Amplifier & I(O) Bus
Row Decoder
Sense Amplifier & I(O) Bus
Row Decoder
Sense Amplifier & I(O) Bus
Row Decoder Memory Array Bank 3
Column Decoder
Column Decoder
Bank 0
Bank 1
Column Decoder
Bank 2
8192 x 512 x 16 Bit
8192 x 512 x 16 Bit
8192 x 512 x 16 Bit
Column Decoder
Memory Array
Memory Array
Memory Array
8192 x 512 x 16 Bit
Input Buffer
Output Buffer
DQ0 - DQ15 Control Logic & Timing Generator
CLK CKE CS RAS CAS WE DQMU DQML VREF *) *) on SSTL versions only
SPB03779
Block Diagram for 16 M x 16 SDRAM (13/9/2 addressing)
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HYB 39S256400/800/160T 256 MBit Synchronous DRAM
Signal Pin Description Pin CLK CKE Type Input Input Signal Polarity Function Pulse Level Positive The system clock input. All of the SDRAM inputs are Edge sampled on the rising edge of the clock. Active High Active Low Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode, Suspend mode, or the Self Refresh mode. CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. During a Bank Activate command cycle, A0 - A12 defines the row address (RA0 - RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0 - An defines the column address (CA0 - CAn) when sampled at the rising clock edge. CAn depends from the SDRAM organization: 64M x 4 SDRAM CAn = CA9, CA11 (Page Length = 2048 bits) 32M x 8 SDRAM CAn = CA9 (Page Length = 1024 bits) 16M x 16 SDRAM CAn = CA8 (Page Length = 512 bits) In addition to the column address, A10 (= AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 (= AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged regardless of the state of BA0 and BA1. If A10 is low, then BA0 and BA1 are used to define which bank to precharge. BA0 BA1 DQx Input Input Output Level Level - - Bank Select (BS) Inputs. Selects which bank is to be active. Data Input/Output pins operate in the same manner as on conventional DRAMs.
CS
Input
Pulse
RAS CAS WE A0 A12
Input
Pulse
Active Low -
Input
Level
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HYB 39S256400/800/160T 256 MBit Synchronous DRAM
Signal Pin Description Pin DQM LDQM UDQM Type Input Signal Polarity Function Pulse Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. One DQM input it present in x4 and x8 SDRAMs, LDQM and UDQM controls the lower and upper bytes in x16 SDRAMs. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity.
VDD, VSS VDDQ VSSQ
Supply - Supply -
- -
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HYB 39S256400/800/160T 256 MBit Synchronous DRAM
Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands.
Operation Bank Active Bank Precharge Precharge All Write
Device State Idle3 Any Any Active3
3 3
CKE n-1 H H H H H H H H H H H H H L H H L L H H
CKE n X X X X X X X X X X X H L H L L H H X X
DQM X X X X X X X X X X X X X X X X X X L H
BS0 BS1 V V X V V V V V X X X X X X X X X X X X
AP = Addr A10 V L H L H L H V X X X X X X X X X X X X V X X V V V V V X X X X X X X X X X X X
CS L L L L L L L L L L H L L H L X H L X H L X X
RAS L L L H H H H L H H X L L X H X X H X X H X X
CAS H H H L L L L L H H X L L X H X X H X X H X X
WE H L L L L H H L H L X H H X X X X X X X L X X
Write with Auto Precharge Active Read Active
Read with Auto Precharge Active3 Mode Register Set No Operation Burst Stop Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit Idle Any Active4 Any Idle Idle Idle (Self Refr.) Active Idle Active5 Active Any (Power Down) Active
Clock Suspend Entry Power Down Entry (Precharge or active standby) Clock Suspend Exit Power Down Exit
Data Write/Output Enable
Data Write/Output Disable Active
Notes 1. V = Valid, X = Don't Care, L = Low Level, H = High Level. 2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3. This is the state of the banks designated by BS0, BS1 signals. 4. Device state is Full Page Burst operation. 5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode cycle device is clock suspend mode.
Semiconductor Group
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HYB 39S256400/800/160T 256 MBit Synchronous DRAM
Address Input for Mode Set (Mode Register Operation)
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus (Ax) Operation Mode CAS Latency BT Burst Length Mode Register (Mx)
Operation Mode
BA1 0 0 Mode burst read / burst write burst read / single write
Burst Type
M3 0 1 Type Sequential Interleave
CAS Latency
M6 M5 M4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved Latency
Burst Length
Length M2 M1 M0 Reserved Reserved 2 3 4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 Reserved 0 1
SPB03941
Sequential 1 2 4 8
Interleave 1 2 4 8
Reserved
Address Input for Mode Set (Mode Register Operation)
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HYB 39S256400/800/160T 256 MBit Synchronous DRAM
Power On and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner.During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power on voltage must not exceed VDD + 0.3 V on any of the input pins or VDD supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 s is required followed by a precharge of both banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. Programming the Mode Register The Mode register designates the operation mode at the read or write cycle. This register is divided into 4 fields. A Burst Length field to set the length of the burst, an Addressing Selection bit to program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency field to set the access time at clock cycle and a Operation mode field to differentiate between normal operation (burst read and burst write) and a special burst read and single write mode. The mode set operation must be done before any activate command after the initial power up. Any content of the mode register can be altered by re-executing the mode set command. All banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the previous table. Read and Write Operation When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 143 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is `2', then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O organization and column addressing. Full page burst operation do not self
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HYB 39S256400/800/160T 256 MBit Synchronous DRAM
terminate once the burst length has been reached. In other words, unlike burst length of 2, 3 or 8, full page burst continues until it is terminated using another command. Similar to the page mode of conventional DRAM's, burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycle is supported. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies an operation change from a read to a write is possible by exploiting DQM to avoid bus contention. When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. Once two or more banks are activated, column to column interleave operation can be done between different pages. Burst Length and Sequence Burst Length 2 4 Starting Address (A2 A1 A0) xx0 xx1 x00 x01 x10 x11 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 Sequential Burst Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 Interleave Burst Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
8
Refresh Mode SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-RAS refresh of conventional DRAMs. All of banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock timing. The mode restores word line after the refresh and no external precharge command is necessary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation.
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HYB 39S256400/800/160T 256 MBit Synchronous DRAM
The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay is required prior to any access command. DQM Function DQM has two functions for data I/O read and write operations. During reads, when it turns to "high" at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks). Suspend Mode During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock and extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend Latency tCSL). Power Down In order to reduce standby power consumption, a power down mode is available. All banks must be precharged and the necessary Precharge delay (tRP) must occur before the SDRAM can enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can't remain in Power Down mode longer than the Refresh period (tREF) of the device. Exit from this mode is performed by taking CKE "high". One clock delay is required for mode entry and exit. Auto Precharge Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock before the last data out for CAS latencies 2, two clocks for CAS latencies 3 and three clocks for CAS latencies 4. If CAS10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation a time delay equal to tWR (Write recovery time) after the last data in. Precharge Command There is also a separate precharge command available. When RAS and WE are low and CAS is high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as shown in the following list. The precharge command can be imposed one clock before the last data out for CAS latency = 2, two clocks before the last data out for CAS latency = 3 and three clocks before the last data out for CAS latency = 4. Writes require a time delay tWR from the last data out to apply the precharge command.
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HYB 39S256400/800/160T 256 MBit Synchronous DRAM
Bank Selection by Address Bits A10 0 0 0 0 1 BA0 0 0 1 1 x BA1 0 1 0 1 x Bank 0 Bank 1 Bank 2 Bank 3 all Banks
Burst Termination Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write command to interrupt an existing burst operation, use a Precharge command to interrupt a burst cycle and close the active bank, or using the Burst Stop command to terminate the existing burst operation but leave the bank open for future Read or Write commands to the same page of the active bank. When interrupting a burst with another Read or Write command care must be taken to avoid DQ contention. The Burst Stop command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop command is registered will be written to the memory.
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HYB 39S256400/800/160T 256 MBit Synchronous DRAM
Absolute Maximum Ratings Operating temperature range .........................................................................................0 to + 70 C Storage temperature range..................................................................................... - 55 to + 150 C Input/output voltage .......................................................................................... - 0.3 to VCC + 0.3 V Power supply voltage VDD / VDDQ ............................................................................. - 0.3 to + 4.6 V Power dissipation....................................................................................................................... 1 W Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operation and Characteristics for LV-TTL Versions TA = 0 to 70 C; VSS = 0 V; VDD, VDDQ = 3.3 V 0.3 V Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 2.0 mA) Output low voltage (IOUT = 2.0 mA) Input leakage current, any input (0 V < VIN < VDDQ, all other inputs = 0 V) Output leakage current (DQ is disabled, 0 V < VOUT < VCC) Symbol min. Limit Values max. 2.0 - 0.3 2.4 - -5 -5 Unit Notes V V V V A A
1, 2 1, 2 3 3
VIH VIL VOH VOL II(L) IO(L)
VCC + 0.3
0.8 - 0.4 5 5
Notes 1. All voltages are referenced to VSS. 2. VIH may overshoot to VCC + 2.0 V for pulse width of < 4ns with 3.3V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3 V. Pulse width measured at 50% points with amplitude measured peak to DC reference. Capacitance TA = 0 to 70 C; VDD = 3.3 V 0.3 V, f = 1 MHz Parameter Input capacitance (CLK) Input capacitance (A0 - A12, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM) Input/Output capacitance (DQ) Symbol min. Values max. 4.0 5.0 6.5 pF pF pF 2.5 2.5 4.0 Unit
CI1 CI2 CIO
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HYB 39S256400/800/160T 256 MBit Synchronous DRAM
Operating Currents TA = 0 to 70 C, VDD = 3.3 V 0.3 V (Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition Operating current tRC = tRCMIN., tCK = tCKMIN. Outputs Open, Burst Lengt = 4, CL = 3 All banks operated in random access All banks operated in ping-pong manner to maximize gapless data access Precharge standby current in Power Down Mode CS = VIH(MIN.), CKE VIL(MAX.) Precharge standby current in Non-Power Down Mode CS = VIH(MIN.), CKE VIH(MAX.) No operating current tCK = min., CS = VIH(MIN.), active state (max. 4 banks) Burst operating current tCK = min., Read command cycling Auto refresh current tCK = min., Auto Refresh command cycling Self refresh current Self Refresh Mode, CKE = 0.2 V Symbol -8/-8B -10 max. Unit Note
3
ICC1
x4 x8 x16 210 210 210 165 165 165 mA mA mA
tCK = min.
ICC2P
2
2
mA
3
tCK = min.
ICC2N
19
16
mA
3
CKE VIH(MIN.) CKE VIL(MAX.)
ICC3N ICC3P ICC4
x4 x8 x16
45 10
40 10
mA mA
3 3
3, 4
210 210 210 240
165 165 165 195
mA mA mA mA
3
ICC5
ICC6
2.5
2.5
mA
3
Notes 3. These parameters depend on the cycle rate. These values are measured at 100 MHz for -8 and at 66 MHz for -10 parts. Input signals are changed once during tCK, excepts for ICC6 and for standby currents when tCK = infinity. 4. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3 and BL = 4 is assumed and the VDDQ current is excluded.
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HYB 39S256400/800/160T 256 MBit Synchronous DRAM
AC Characteristics 1, 2, 3 TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V, tT = 1 ns Parameter Symb. -8 min. Clock and Clock Enable Clock Cycle Time CAS Latency = 3 tCK CAS Latency = 2 Clock Frequency CAS Latency = 3 tCK CAS Latency = 2 Access Time from Clock CAS Latency = 3 tAC CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Transition time Setup and Hold Times Input Setup Time Input Hold Time CKE Setup Time CKE Hold Time Mode Register Setup time 8 10 - - - - 3 3 0.5 - - 125 100 6 6 - - 10 3 3 0.5 10 12 - - 100 83 6 7 - - 10 10 15 - - - - 3 3 0.5 - - 100 66 7 8 - - 10 ns ns MHz MHz
2, 4
Limit Values -8B -10 max. max. min. max. min.
Unit Note
ns ns ns ns ns
tCH tCL tT
tIS tIH tCKS tCKH tRSC
2 1 2 1 16 0
- - - - - 8
2 1 2 1 20 0
- - - - - 10
2.5 1 2.5 1 20 0
- - - - - 10
ns ns ns ns ns ns
5 5 5 5
Power Down Mode Entry Time tSB Common Parameters Row to Column Delay Time Row Precharge Time Row Active Time Row Cycle Time Activate (a) to Activate (b) Command period CAS (a) to CAS (b) Command period
tRCD tRP tRAS tRC tRRD tCCD
20 20 50 70 16 1
- - - - -
20 30 80 20 1
- - - - -
30 30 90 20 1
- - - - -
ns ns ns ns CLK
6 6 6 6 6
100k 60
100k 60
100k ns
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HYB 39S256400/800/160T 256 MBit Synchronous DRAM
AC Characteristics 1, 2, 3 (cont'd) TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V, tT = 1 ns Parameter Symb. -8 min. Refresh Cycle Refresh Period (8192 cycles) Self Refresh Exit time Read Cycle Data Out Hold time Data Out to Low Impedance time Data Out to High Impedance time DQM Data Out Disable latency Write Cycle Data Input to Precharge DQM Write Mask Latency Limit Values -8B -10 max. max. min. max. min. Unit Note
tREF tSREX
- 10
64 -
- 10
64 -
- 10
64 -
ms ns
tOH tLZ tHZ tDQZ
3 0 3 -
- - 8 2
3 0 3 -
- - 10 2
3 0 3 -
- - 10 2
ns ns ns CLK
2
8
tWR tDQW
2 0
- -
2 0
- -
2 0
- -
CLK CLK
Semiconductor Group
18
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
Notes for AC Parameters 1. For proper power-up see the operation section of this data sheet. 2. AC timing tests for LV-TTL versions have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in Figure 1. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with an input signal of 1 V/ns edge rate between 0.8 V and 2.0 V.
t CH
CLOCK 2.4 V 0.4 V
t CL t SETUP
INPUT
tT
t HOLD
1.4 V
t AC t LZ
OUTPUT
t AC t OH
I/O
1.4 V
50 pF
t HZ
SPT03404
Measurement conditions for tAC and tOH
Figure 1 3. AC timing test conditions for SSTL_3 versions
+Vtt 50
Z = 50
Output
30 pF
SPS03410
Figure 2 Termination voltage Reverence Level of Output Signals (VREF) Output Load Transition Time (Rise and Fall) of Input Signals Reference Level of Input Signals (VREF) Semiconductor Group 19 0.45 x VCCQ 0.45 x VCCQ see Figure 2 1 ns 0.45 x VCCQ 1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
4. If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter. 5. If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter. 6. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered.
Semiconductor Group
20
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
Package Outlines Plastic Package P-TSOPII-54 (400 mil, 0.8 mm lead pitch) Thin small outline package, SMD
0.10.05 10.05
155 10.160.13 2)
0.8 155 0.35 +0.1 -0.05
3)
0.15 +0.06 -0.03
0.5 0.1 11.76 0.2
26x 0.8 = 20.8
0.1 54x 0.2 M 54x
54
28
6 max
1 2.5 max 22.220.13 1) Index Marking
1) 2)
27
GPX09039
Does not include plastic or metal protrusion of 0.15 max per side Does not include plastic protrusion of 0.25 max per side 3) Does not include dambar protrusion of 0.13 max per side
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 21
Dimensions in mm 1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
Timing Diagrams 1 2 3 4 4.1 4.2 4.3 5 6 6.1 6.2 7 7.1 7.2 8 8.1 8.2 9 9.1 9.2 10 11 12 12.1 12.2 12.3 12.4 13 14 15 16 16.1 16.2 Bank Activate Command Cycle Burst Read Operation Read Interrupted by a Read Read to Write Interval Read to Write Interval Minimum Read to Write Interval Non-Minimum Read to Write Interval Burst Write Operation Write and Read Interrupt Write Interrupted by a Write Write Interrupted by a Read Burst Write and Read with Auto Precharge Burst Write with Auto Precharge Burst Read with Auto Precharge Burst Termination Termination of a full Page Burst Read Operation Termination of a full Page Burst Write Operation AC Parameters AC Parameters for a Write Timing AC Parameters for a Read Timing Mode Register Set Power on Sequence and Auto Refresh (CBR) Clock Suspension (Using CKE) Clock Suspension During Burst Read CAS Latency = 2 Clock Suspension During Burst Read CAS Latency = 3 Clock Suspension During Burst Write CAS Latency = 2 Clock Suspension During Burst Write CAS Latency = 3 Power Down Mode and Clock Suspend Self Refresh (Entry and Exit) Auto Refresh (CBR) Random Column Read (Page within same Bank) CAS Latency = 2 CAS Latency = 3
Semiconductor Group
22
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
Timing Diagrams (cont'd) 17 17.1 17.2 18 18.1 18.2 19 19.1 19.2 20 20.1 20.2 21 21.1 21.2 22 22.1 22.2 Random Column Write (Page within same Bank) CAS Latency = 2 CAS Latency = 3 Random Row Read (Interleaving Banks) with Precharge CAS Latency = 2 CAS Latency = 3 Random Row Write (Interleaving Banks) with Precharge CAS Latency = 2 CAS Latency = 3 Full Page Read Cycle CAS Latency = 2 CAS Latency = 3 Full Page Write Cycle CAS Latency = 2 CAS Latency = 3 Precharge Termination of a Burst CAS Latency = 2 CAS Latency = 3
Semiconductor Group
23
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
1. Bank Activate Command Cycle
(CAS latency = 3)
T0 CLK T1 T T T T T
Address
Bank B Row Addr.
Bank B Col. Addr.
Bank A Row Addr.
Bank B Row Addr.
t RCD
Command
Bank B Activate
t RRD
NOP
Write B with Auto Precharge
NOP
Bank A Activate
NOP
Bank B Activate
t RC
"H" or "L"
SPT03784
Semiconductor Group
24
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
2. Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Read A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
SPT03712
Semiconductor Group
25
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
3. Read Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Read A
Read B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
SPT03713
Semiconductor Group
26
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
4. Read to Write Interval 4.1. Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0 CLK Minimum delay between the Read and Write Commands = 4 + 1 = 5 cycles DQMx Write latency t DQW of DQMx T1 T2 T3 T4 T5 T6 T7 T8
t DQZ
Command NOP Read A NOP NOP NOP NOP Write B NOP NOP
DQ's
DOUT A0
DIN B0
DIN B1
DIN B2
Must be Hi-Z before the Write Command "H" or "L"
SPT03787
Semiconductor Group
27
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
4.2. Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
DQMx
Write latency t DQW of DQMx
t DQZ
1 Clk Interval Command NOP
Bank A Activate
NOP
NOP
Read A
Write A
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's
Must be Hi-Z before the Write Command DIN A0 DIN A1 DIN A2 DIN A3
"H" or "L"
SPT03413
4.3. Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
DQM
t DQW t DQZ
Command
NOP
Read A
NOP
NOP
Read A
NOP
Write B
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's "H" or "L"
Must be Hi-Z before the Write Command DOUT A0 DOUT A1 DIN B0 DIN B1 DIN B2
DOUT A0
DIN B0
DIN B1
DIN B2
SPT03940
Semiconductor Group
28
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
5. Burst Write Operation
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
NOP
Write A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQ's
DIN A0
DIN A1
DIN A2
DIN A3
don't care
The first data element and the Write are registered on the same clock edge.
Extra data is ignored after termination of a Burst.
SPT03790
Semiconductor Group
29
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
6. Write and Read Interrupt 6.1. Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
NOP
Write A
Write B
NOP
NOP
NOP
NOP
NOP
NOP
1 Clk Interval DQ's DIN A0 DIN B0 DIN B1 DIN B2 DIN B3
SPT03791
6.2. Write Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
NOP
Write A
Read B
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's
DIN A0
don't care
DOUT B0 DOUT B1 DOUT B2 DOUT B3
DIN A0
don't care
don't care
DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from the DQ's at least one clock cycle before the Read data appears on the outputs to avoid data contention.
SPT03719
Input data for the Write is ignored.
Semiconductor Group
30
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
7. Burst Write and Read with Auto Precharge 7.1. Burst Write with Auto Precharge
(Burst Length = 2, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Bank A Active
NOP
NOP
Write A Auto Precharge
NOP
NOP
NOP
NOP
NOP
t WR
DQ's DIN A0 DIN A1
t RP
Begin Auto Precharge Bank can be reactivated after t RP
SPT03909
7.2. Burst Read with Auto Precharge
(Burst Length = 4, CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Read A with AP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t RP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3
t RP
DOUT A0 DOUT A1 DOUT A2 DOUT A3 Begin Auto Precharge Bank can be reactivated after t RP
SPT03721
Semiconductor Group
31
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
8. Burst Termination 8.1. Termination of a Full Page Burst Read Operation
(CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
Read A
NOP
NOP
NOP
Burst Terminate
NOP
NOP
NOP
NOP
CAS latency = 2 t CK2 , DQ's CAS latency = 3 t CK3 , DQ's
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3 The burst ends after a delay equal to the CAS latency.
SPT03722
8.2. Termination of a Full Page Burst Write Operation
(CAS latency = 2, 3)
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
NOP
Write A
NOP
NOP
Burst Terminate
NOP
NOP
NOP
NOP
CAS latency = 2, 3 DQ's
DIN A0
DIN A1
DIN A2
don't care
Input data for the Write is masked.
SPT03419
Semiconductor Group
32
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
9. AC Parameters 9.1. AC Parameters for Write Timing
Burst Length = 4, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CH t CL
CKE
t CK2
t CKS
t CS t CH
Begin Auto Precharge Bank A
Begin Auto Precharge Bank B
t CKH
CS RAS CAS WE BS
t AH
AP
RAx RBx RAy RAz RBy
t AS
Addr. DQM
RAx CAx RBx CBx RAy RAy RAz RBy
t DS t RCD t RC
DQ Hi-Z
t DH
t WR t RP t RRD
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3
Activate Command Bank A Write with Auto Precharge Command Bank A
Activate Command Bank B Write with Auto Precharge Command Bank B
Activate Command Bank A
Write Command Bank A
Precharge Command Bank A
Activate Command Bank A
Activate Command Bank B
SPT03910
Semiconductor Group
33
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
9.2. AC Parameters for a Read Timing
y
Burst Length = 2, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
t CH t CL
CKE
t CK2 t CKH t CS
Begin Auto Precharge Bank A Begin Auto Precharge Bank B
t CKS t CH
CS RAS CAS WE BS
t AH
AP RAx RBx RAy
t AS
Addr. RAx CAx RBx RBx RAy
t RRD t RAS
DQM
t RC t AC2 t LZ t RCD t OH t AC2 t HZ
Ax1 Bx0 Bx1
t HZ
t RP
DQ
Hi-Z
Ax0
Activate Command Bank A
Read with Auto Precharge Command Bank A
Activate Command Bank B
Read with Auto Precharge Command Bank B
Precharge Command Bank A
Activate Command Bank A
SPT03911
Semiconductor Group
34
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
10. Mode Register Set
CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
t RSC
CS RAS CAS WE BS0, BS1 A10, A11 Address Key A0-A9
Precharge Command All Banks Mode Register Set Command
Any Command
SPT03912
Semiconductor Group
35
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
11. Power on Sequence and Auto Refresh (CBR)
T0
~ ~
T1
T2
T3
T4
T5
T6
T7
T8
~ ~
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
~ ~
CKE
High Level is required
~ ~
~ ~
Minimum of 8 Refresh Cycles are required
~ ~
2 Clock min.
CS RAS CAS WE BS AP
~ ~ ~ ~ ~ ~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~
~ ~
~~ ~~
~~ ~~
~~ ~~
~~ ~~
Address Key
~ ~ ~~ ~~ ~~ ~~
Addr. DQM
t RP
DQ
~ ~ ~ ~
~ ~
t RC
Hi-Z
Precharge Command All Banks Inputs must be stable for 200 s 1st Auto Refresh Command
8th Auto Refresh Command
Mode Register Set Command
Any Command
SPT03913
Semiconductor Group
36
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
12. Clock Suspension (Using CKE) 12.1. Clock Suspension During Burst Read CAS Latency = 2
Burst Length = 4, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr. DQM
RAx RAx CAx
t CSL t CSL
DQ Hi-Z Ax0 Ax1 Ax2
t CSL
Ax3
t HZ
Read Activate Command Command Bank A Bank A
Clock Suspend 1 Cycle
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
SPT03914
Semiconductor Group
37
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
12.2. Clock Suspension During Burst Read CAS Latency = 3
Burst Length = 4, CAS Latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK3
CKE CS RAS CAS WE BS AP Addr. DQM
RAx RAx CAx
t CSL
t CSL
t CSL t HZ
DQ
Hi-Z
Ax0
Ax1
Ax2
Ax3
Activate Command Bank A
Read Command Bank A
Clock Suspend 1 Cycle
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
SPT03915
Semiconductor Group
38
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
12.3. Clock Suspension During Burst Write CAS Latency = 2
Burst Length = 4, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3
RAx RAx CAx
Activate Command Bank A
Clock Suspend 1 Cycle Write Command Bank A
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
SPT03916
Semiconductor Group
39
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
12.4. Clock Suspension During Burst Write CAS Latency = 3
Burst Length = 4, CAS Latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK3
CKE CS RAS CAS WE BA A8/AP Addr. DQMx DQ Hi-Z DAx0 DAx1 DAx2 DAx3
RAx RAx CAx
Activate Command Bank A
Clock Suspend 1 Cycle Write Command Bank A
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
SPT03917
Semiconductor Group
40
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
13. Power Down Mode and Clock Suspend
Burst Length = 4, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr. DQM
RAx RAx
t CKS
t CKS
CAx
t HZ
DQ Hi-Z Ax0 Ax1 Ax2 Ax3
Activate Command Bank A
Active Standby
Read Command Bank A
Clock Mask Start
Clock Mask End
Precharge Command Bank A
Precharge Standby
Any Command
Clock Suspend Mode Entry
Clock Suspend Mode Exit
Power Down Mode Entry
Power Down Mode Exit
SPT03918
Semiconductor Group
41
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
14. Self Refresh (Entry and Exit)
T0 CLK
T1
T2
T3
T4
T5
~ ~ ~ ~
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CKS
CS RAS CAS WE BS AP Addr.
~ ~
CKE
t CKS
~ ~
~~ ~~
~~ ~~
~~ ~~
~~ ~~
~~ ~~
~~ ~~
~ ~
t SREX
~ ~
DQM Hi-Z
t RC
DQ
All Banks must be idle
Self Refresh Entry
~ ~
Begin Self Refresh Exit Command Self Refresh Exit Command issued Self Refresh Exit
Any Command
SPT03919
Semiconductor Group
42
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
15. Auto Refresh (CBR)
Burst Length = 4, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx
DQM DQ Hi-Z
t RP
t RC (Minimum Interval)
t RC
Ax0 Ax1 Ax2 Ax3
Precharge Command All Banks
Auto Refresh Command
Auto Refresh Command
Activate Command Bank A
Read Command Bank A
SPT03920
Semiconductor Group
43
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
16. Random Column Read (Page within same Bank) 16.1. CAS Latency = 2
Burst Length = 4, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Az1 Az2 Az3
RAw RAw CAw CAx CAy RAz RAz CAz
Activate Command Bank A
Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
SPT03921
Semiconductor Group
44
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
16.2. CAS Latency = 3
Burst Length = 4, CAS Latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK3
CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
RAw RAw CAw CAx CAy RAz RAz CAz
Activate Command Bank A
Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A SPT03922
Semiconductor Group
45
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
17. Random Column Write (Page within same Bank) 17.1. CAS Latency = 2
Burst Length = 4, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 DBz3
RAw RAw CAw CAx CAy RAz RAz CAz
Activate Command Bank A
Write Command Bank B
Write Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Read Command Command Bank B Bank B
SPT03923
Semiconductor Group
46
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
17.2. CAS Latency = 3
Burst Length = 4, CAS Latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK3
CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1
RBz RBz CBz CBx CBy RBz RBz CBz
Activate Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Command Bank B
Write Command Bank B SPT03924
Semiconductor Group
47
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
18. Random Row Read (Interleaving Banks) with Precharge 18.1. CAS Latency = 2
Burst Length = 8, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr.
RBx RBx CBx RAx RAx CAx RBy RBy CBy
High
t RCD
DQM
t RP
t AC2
DQ Hi-Z Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 By1
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Precharge Activate Command Command Bank B Bank B Read Command Bank A
Read Command Bank B
SPT03925
Semiconductor Group
48
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
18.2. CAS Latency = 3
Burst Length = 8, CAS Latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK3
CKE CS RAS CAS WE BS AP Addr.
RBx RBx CBx RAx RAx CAx RBy RBy CBy
High
t RCD
DQM DQ Hi-Z
t AC3
t RP
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Read Command Bank A
Precharge Command Bank B
Activate Command Bank B
Read Command Bank B
Precharge Command Bank A
SPT03926
Semiconductor Group
49
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
19. Random Row Write (Interleaving Banks) with Precharge 19.1. CAS Latency = 2
Burst Length = 8, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx RBx RBx CBx RAy RAy CAy
High
t RCD
DQM DQ Hi-Z
t WR
t RP
t WR
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B Precharge Command Bank A
Activate Command Bank A
Precharge Command Bank B Write Command Bank A
SPT03927
Semiconductor Group
50
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
19.2. CAS Latency = 3
Burst Length = 8, CAS Latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK3
CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx RBx RBx CBx RAy RAy CAy
High
t RCD
DQM DQ Hi-Z
t WR
t RP
t WR
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B
Precharge Command Bank A
Activate Command Bank A
Write Command Bank A
Precharge Command Bank B
SPT03928
Semiconductor Group
51
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
20. Full Page Read Cycle 20.1. CAS Latency = 2
Burst Length = Full Page, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6
~ ~ ~ ~
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx RBx RBx
~ ~ ~~ ~~ ~ ~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~
High
~ ~
~ ~
RBy CBx RBy
t RP
~~ ~~
DQM DQ Hi-Z
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
~ ~
Ax Ax +1 Ax + 2 Ax - 2
Ax -1
Ax
Ax+1 Bx
Bx+1 Bx+2 Bx + 3 Bx+ 4 Bx+ 5 Bx + 6
Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval.
Burst Stop Precharge Command Command Bank B Activate Command Bank B
SPT03929
Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
Semiconductor Group
52
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
20.2. CAS Latency = 3
Burst Length = Full Page, CAS Latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
~ ~ ~ ~
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK3
CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx RBx RBx
~ ~ ~~ ~~ ~ ~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~
High
~ ~
~ ~
RBy CBx RBy
t RRD
~~ ~~
DQM DQ Hi-Z Ax
Activate Command Bank A Read Command Bank A
Activate Command Bank B
~ ~
Ax +1 Ax+ 2 Ax - 2
Ax -1
Ax
Ax +1 Bx
Bx +1 Bx +2 Bx + 3 Bx+ 4 Bx + 5
Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval.
Burst Stop Precharge Command Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
Activate Command Bank B
SPT03930
Semiconductor Group
53
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
21. Full Page Write Cycle 21.1. CAS Latency = 2
Burst Length = Full Page, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5
~ ~ ~ ~
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi-Z
RAx RAx CAx RBx RBx
~ ~ ~~ ~~ ~ ~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~
High
~ ~
~ ~
RBy CBx RBy
Activate Command Bank A
Write Command Bank A
~ ~
DAx DAx+1 DAx+2 DAx+3 DAx- 1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+ 3 DBx+ 4 DBx+ 5 DBx+6
~~ ~~
Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval.
Write Command Bank B
Data is ignored.
Burst Stop Command
Activate Command Bank B
Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
Precharge Command Bank B
SPT03931
Semiconductor Group
54
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
21.2. CAS Latency = 3
Burst Length = Full Page, CAS Latency = 3 T0 CLK T1 T2 T3 T4 T5 T6
~ ~ ~ ~
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK3
CKE CS RAS CAS WE BS AP Addr. DQM DQ Hi Z
RAx RAx CAx RBx RBx
~ ~ ~~ ~~ ~ ~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~
High
~ ~
~ ~
RBy CBx RBy
Activate Command Bank A Write Command Bank A
Activate Command Bank B
~ ~
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+ 1 DBx DBx+1 DBx+ 2 DBx+ 3 DBx+ 4 DBx+5
~~ ~~
Write Command Bank B
Data is ignored.
Burst Stop Command Precharge Command Bank B
Activate Command Bank B
The burst counter wraps from the highest order page address back to zero during this time interval.
Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
SPT03932
Semiconductor Group
55
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
22. Precharge Termination of a Burst 22.1. CAS Latency = 2
Burst Length = 8 or Full Page, CAS Latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE CS RAS CAS WE BS AP Addr.
RAx RAx CAx RAy RAy CAy RAz RAz CAz
High
t RP
DQM
t RP
t RP
DQ
Hi Z
DAx0 DAx1 DAx2 DAx3
Ay0 Ay1 Ay2
Az0 Az1 Az2
Activate Command Bank A
Write Command Bank A Precharge Termination of a Write Burst. Write Data is masked.
Precharge Command Bank A Activate Command Bank A
Read Command Bank A
Precharge Command Bank A Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Precharge Termination of a Read Burst.
SPT03933
Semiconductor Group
56
1998-10-01

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